(a) Field of the Invention
The present invention relates to a semiconductor device with a metal line and a method of forming the same. More particularly, the present invention relates to a method of forming a structure of an interlayer insulation layer.
(b) Description of the Related Art
Generally, metal lines in a semiconductor device connect circuits in a semiconductor substrate through an electrical connection and pad connection between semiconductor devices by using a thin metal layer composed of aluminum, an aluminum alloy, or copper.
In order to form such metal lines, a contact hole is formed by selectively etching an insulation layer, and a metal plug filling in the contact hole is formed by using a barrier metal and tungsten. The contact hole is formed so as to connect a device electrode and a pad which are separated by an insulation layer.
In addition, a thin metal layer is formed on the metal plug, and then a metal line for connecting a device electrode and a pad is finally formed by patterning the thin metal layer
Recently, as semiconductor devices have become more miniaturized, a CD (critical dimension) of a metal line has also become smaller. However, even if a photolithography process is mainly used for patterning a metal line, it is very difficult to form a metal line having a fine pattern. Therefore, a damascene process is frequently used in order to easily form a metal line having a fine pattern.
According to a damascene process, a metal line having a fine pattern can be formed by the following processes. Firstly, a tungsten plug is formed in a contact hole at an insulation layer, and then an upper insulation layer such as an oxide layer is deposited on the insulation layer. Subsequently, only a portion of the upper insulation layer in the region where a metal line pattern will be formed is removed by a photolithography process, and then a thin metal layer is deposited on the entire surface of the upper insulation layer. A metal line is then formed by planarizing the thin metal film.
Recently, a dual damascene technique has been introduced for forming the metal wiring for contacting the lower conductive layer without forming the metal plug such as a tungsten plug.
An insulation layer required for forming a metal line may be composed of a USG (un-doped silicate glass) or FSG (fluorine silicate glass). However, as semiconductor devices have become more highly integrated, the thickness and width of an insulation layer thereof have been reduced. Therefore, interference between electrical signals transmitted through a metal line may frequently occur.
In addition, since the above-mentioned insulation layer has a dielectric constant of 3.9 to 4.2, the operation speed of a semiconductor device may be deteriorated due to the high dielectric constant.
On the other hand, when an insulation layer having a low dielectric constant, such as one made from CSG (carbonate silicate glass), FC (fluorine amorphous carbon), or HSQ (hydrogen silsesquioxane), is used for forming a metal line, yield of semiconductor devices may be deteriorated and manufacturing costs may be increased because the insulation layer having a low dielectric constant shows an unstable quality of the layer and because an additional process, such as a liner process, is required for preventing damage caused by a subsequent thermal process.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form part of the prior art with respect to the present invention.